Nanotechnology Now - Press Release: Leti Demonstrates Ultra-scaled Self-aligned Split-gate Memory Cell With 16nm Gate Length: Benefits Especially for Contactless Applications Include Larger Memory Window, Improved Control of Spacer Memory Gate Shape and Length, And Better Functionality

Home > Press > Leti Demonstrates Ultra-scaled Self-aligned Split-gate Memory Cell With 16nm Gate Length: Benefits Especially for Contactless Applications Include Larger Memory Window, Improved Control of Spacer Memory Gate Shape and Length, And Better Functionality

TEM images of ultra-scaled self-aligned split-gate device, with a memory gate length of 16nm.

Abstract:
CEA-Leti announced today it has fabricated ultra-scaled split-gate memories with gate length of 16nm, and demonstrated their functionality, showing good writing and erasing performances with memory windows over 6V.

Leti Demonstrates Ultra-scaled Self-aligned Split-gate Memory Cell With 16nm Gate Length: Benefits Especially for Contactless Applications Include Larger Memory Window, Improved Control of Spacer Memory Gate Shape and Length, And Better Functionality

Grenoble, France | Posted on March 13th, 2014

The devices provide several benefits especially for contactless memory applications, such as enlargement of the memory window and increased functionality. Also because of an optimised fabrication step, the devices allow better control of spacer memory gate shape and length.

Split-gate flash memories are made of two transistors: an access transistor and a memory transistor with a charge-trapping layer (nitride, Si nanocrystals etc.). Split-gate architectures use a low-access voltage and minimize drain current during programming, which leads to a decrease of the programming power compared to standard one-transistor NOR memories. Because programming energy decreases when memory gate length decreases, ultra-scaling is particularly relevant for contactless applications.

Memory gate has been reduced down to 16nm thanks to a poly-Si spacer formed on the sidewall of the select transistor. This approach avoids costly lithography steps during fabrication and solves misalignment issues, which are responsible for a strong variation of the electrical performances, such as the memory window.

The main challenges of this self-aligned technology concern the precise control of the spacer memory gate shape and of the memory gate length. Spacer gate has to fulfil two difficult requirements: being as flat as possible in order to get a silicidation surface as large as possible while insuring a functional contact, and getting a steep edge in order to control the drain-junction doping.

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About CEA-Leti
By creating innovation and transferring it to industry, Leti is the bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. Backed by its portfolio of 2,200 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched more than 50 startups. Its 8,000m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. Leti’s staff of more than 1,700 includes 200 assignees from partner companies. Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo.

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Contacts:
CEA-Leti
+33 4 38 78 02 26

Agency
+33 6 64 52 81 10

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