Nanotechnology Now - Press Release: Imec develops procedure for carrier profiling in nanowire-based transistors

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Quantitative 2D-carrier distribution for nanowire diameters of 400nm and 100nm. The difference in drain doping is reflected in the TFET off current.

Abstract:
Imec's researchers have developed a methodology to quantitatively map the distribution of active dopants in confined 3D-volumes. This is an important step towards in-depth understanding of transistors based on semiconductor nanowires. The new methodology is based on high-vacuum scanning spreading resistance microscopy (HV-SSRM).

Imec develops procedure for carrier profiling in nanowire-based transistors

Leuven, Belgium | Posted on June 16th, 2011

Semiconductor nanowires are one of the most promising building blocks for future nanoelectronic devices such as transistors, sensors and solar cells. Nanowire-based tunnel field-effect transistors (TFETs), for example, are widely seen as potential successors of standard MOSFETs, due to the absence of a 60mV/dec sub-threshold swing limitation and reduced short-channel effects.

But to optimize the fabrication processes for such high-performance devices, it is necessary to have a thorough understanding of the active dopant (carrier) distribution. Therefore, researchers from imec have recently extended the applicability of HV-SSRM as a metrology tool for carrier mapping to fully integrated nanowire-based transistors.

Applying HV-SSRM to Si-nanowire-based tunnel-FETs, the team identified a diameter-dependent dopant-deactivation mechanism. This mechanism occurs in small 3D structures only and cannot be predicted using standard process simulation tools. It could be shown experimentally and through device simulations that this phenomenon directly impacts the device characteristics. The validity of the technique is proved by the observance of the diameter dependency of the carrier distribution in the nanowire top-section. This results from a tilted ion implantation step and is perfectly in agreement with results from process simulations.

Scanning spreading resistance microscopy (SSRM) is a technique with a unique combination of high spatial resolution (1 to 3nm) and high sensitivity. SSRM is based on atomic force microscopy and was invented by W. Vandervorst et al. at imec in 1994. During the last decade, it has evolved into the method of choice for carrier profiling in planar MOS transistors. With this work, imec applied HV-SSRM to Si-nanowire-based tunnel-FETs, proving its validity to study carrier distribution in semiconductor nanowires. It also showed that HV-SSRM is capable of revealing physical phenomena which are present in small, 3D structures only, and which cannot be predicted by blanket experiments. Such information is essential for the process development of future nanowire-based devices.

This study has been published in Nanotechnology - issue 18 (volume 22). An illustration from the study was selected for the cover of the journal.

The paper can be accessed on iopscience.iop.org/0957-4484/22/18/185701.

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About Imec
Imec performs world-leading research in nano-electronics and nano-technology. Its staff of more than 1,900 people includes over 500 industrial residents and guest researchers. Imec’s research is applied in better healthcare, smart electronics, sustainable energy, and safer transport.

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