Nanotechnology Now - Press Release: Cadence Low-Power Solution Enables Legend Silicon to Achieve 90nm First Silicon Success

Home > Press > Cadence Low-Power Solution Enables Legend Silicon to Achieve 90nm First Silicon Success

Abstract:
Legend Selects Cadence as Primary EDA Supplier, Leverages Low-Power Solution for Advanced DTV and Wireless Design

Cadence Low-Power Solution Enables Legend Silicon to Achieve 90nm First Silicon Success

SAN JOSE, CA | Posted on October 27th, 2008

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that Legend Silicon, a leading technology company delivering semiconductor solutions for terrestrial digital TV (DTV), has taped out a 90-nanometer design by leveraging the Cadence® Low-Power Solution to achieve first silicon success. Legend Silicon has selected Cadence as their primary EDA supplier for 65 and 45 nanometer designs, and will adopt the complete Cadence Low-Power Solution, affirming the commitment from Cadence to enable innovation and strength in low-power designs.

With Cadence software, Legend Silicon taped out a challenging, multi-million gate 90-nanometer DTV design, which is now in volume production. As a result, Legend Silicon continues to offer leading-edge digital television products to its customers.

"Leveraging Cadence design, verification and implementation technologies, Legend Silicon is able to beat an aggressive design schedule and achieve first silicon success," said Dr. Lin Yang, the CTO of Legend Silicon. "By selecting Cadence as our primary EDA vendor for 65 and 45 nanometers and collaborating closely together, we will be able to maintain and sharpen our competitive edge in DTV and wireless fields, and provide better solutions to our customers within a shorter timeframe."

As the primary EDA supplier, Cadence will provide Legend Silicon with advanced EDA technologies for 45-nanometer/65-nanometer low-power hierarchical flow. Legend Silicon will also adopt the Common Power Format (CPF)-based Cadence Low-Power Solution, consisting of Incisive® Enterprise Simulator, Encounter® Conformal® Low Power, Encounter RTL Compiler global synthesis, Encounter(TM) Digital Implementation System, and Encounter Power System.

"Cadence is committed to enabling innovation and success for customers," said Lung Chu, president of Cadence Asia Pacific and corporate VP of Cadence. "The proven Cadence Low-Power Solution based on CPF will enable Legend Silicon to realize the power-reduction benefits of advanced low-power management strategies, while speeding up time to market, improving productivity and reducing risk in their design methodology."

The Cadence Low-Power Solution is the industry's first complete flow that leverages the Common Power Format to integrate logic design, verification, and implementation technologies. It is already proven on multiple tapeouts and multiple applications; designers have realized up to a twofold productivity increase with an average of 40 percent power savings using this flow.

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About Cadence Design Systems, Inc.
Cadence enables global electronic-design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

Cadence, Incisive, Conformal, Encounter, and VoltageStorm are registered trademarks, and the Cadence logo and SoC Encounter are trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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Contacts:
Dan Holden
Cadence Design Systems, Inc.
Direct: 408-944-7457

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