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July 2nd, 2007

Nanotechnology fabrication depends on sophisticated simulation tools

Abstract:
Continuing miniaturization has moved the semiconductor industry into the nano realm with leading chip manufacturers well on their way to CPUs using 32nm process technology (expected by 2009). There are some real challenges ahead for chip designers, particularly in moving deeper and deeper into the nanoscale, where at some point in the near future they will reach physical limits of the traditional logic MOSFET (metal-oxide-semiconductor field-effect transistor) structure. In addition to physical barriers, semiconductor companies will also reach economic barriers where profitability will be squeezed hard in view of the exorbitant costs of building the necessary manufacturing capabilities if present day technologies are extrapolated. Quantum and coherence effects, high electric fields creating avalanche dielectric breakdowns, heat dissipation problems in closely packed structures and the relevance of single atom defects are all roadblocks along the current road of miniaturization. Enter nanoelectronics (note that microelectronics, even if the gate size of the transistor is below 100 nm, is not an implementation of nanoelectronics, as no new qualitative physical property related to reduction in size are being exploited). Its goal is to process, transmit and store information by taking advantage of properties of matter that are distinctly different from macroscopic properties. Understanding nanoscale transport and being able to model and simulate nanodevices requires an entirely new generation of simulation tools and techniques.

Source:
nanowerk.com

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