Nanotechnology Now - Press Release: SEMATECH Advances Device Processing Techniques to Enable III-V Manufacturing: Results show significant progress in developing a low-cost process technology to deposit III-Vs on top of silicon

Home > Press > SEMATECH Advances Device Processing Techniques to Enable III-V Manufacturing: Results show significant progress in developing a low-cost process technology to deposit III-Vs on top of silicon

Abstract:
SEMATECH announced today that researchers have made significant advances in post-epitaxial growth backside clean processing that will prepare III-V technology for high-volume manufacturing. The research leading to these accomplishments was conducted at SEMATECH's facilities at the College of Nanoscale Science and Engineering (CNSE) in Albany, NY.

SEMATECH Advances Device Processing Techniques to Enable III-V Manufacturing: Results show significant progress in developing a low-cost process technology to deposit III-Vs on top of silicon

Albany, NY | Posted on June 27th, 2013

Following a two-year effort to improve process parameters and validating III-V on 200 mm Si VLSI process flows, technologists have identified the key mechanisms to enable a robust backside cleaning process and made significant progress in reducing the likelihood of process cross-contamination that could impact a high-volume manufacturing line. This important milestone was presented during SEMATECH's Surface Preparation and Cleaning Conference held recently in Austin, Texas.

Furthermore, SEMATECH has developed systematic experiments to identify the key mechanisms of backside contamination, which were then used to engineer robust backside clean process using standard high-volume manufacturing toolsets. At the same time, researchers assessed the environmental, safety and health (ESH) risks of applying and processing compound semiconductor films on silicon dioxide wafers.

"In order to drive cost-effective compliance solutions, SEMATECH is developing new testing and analysis methodologies to evaluate ESH impacts of novel materials," said Hsi-An Kwong, SEMATECH's ESH Technology Center program manager. "After conducting a process analysis of III-V manufacturing line, we were able to identify potential ESH risks, including generation of arsine and arsenic compounds, and develop protocols to help mitigate the impact to environment and safety."

Supported by the conventional Si CMOS processing capabilities of CNSE, SEMATECH researchers are now working jointly with chipmakers, equipment and materials suppliers and universities on the ESH and contamination challenges of processing III-V materials in a 300 mm fab in order to enable safe implementation of III-V technology for high-volume manufacturing.

III-V compound semiconductors are considered valid candidates as building blocks for the implementation of high-performance, low-power logic devices beyond the 10 nm technology node. To be truly competitive, III-V based technology must be monolithically integrated with Si in order to benefit from the existing Si-based semiconductor processing. For successful introduction into a Si manufacturing line, hetero-integrated III-V on Si wafers must be processed with a backside clean and capping processes.

"Through the success of our research and development efforts, SEMATECH is developing manufacturable solutions and practical implementation approaches to enable the fabrication of logic devices and systems on chips with diverse and improved functionalities," said Paul Kirsch, director of Front End Processes (FEP) at SEMATECH.

For over half a century, silicon-based materials have been the basic layers used in the manufacturing of CMOS transistors; however, these staple materials, as well as materials derived from silicon such as insulators and contact metals, are reaching their limits as the industry looks to lower power dissipation in CMOS devices and as scaling approaches the physical limits of silicon transistors. SEMATECH's FEP program is exploring innovative materials, new transistor structures and alternative non-volatile memories to address key aspects of system-level performance, power, variability and cost to help accelerate innovation in the continued scaling of logic and memory applications.

"The backside clean step is a key component of successful introduction of III-V material to a 300 mm high-volume manufacturing line," said Chris Hobbs, SEMATECH's FEP program manager. "Success at this step is critical to ensure contamination control through subsequent toolsets."

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About SEMATECH
For over 25 years, SEMATECHŽ, the international consortium of leading semiconductor device, equipment, and materials manufacturers, has set global direction, enabled flexible collaboration, and bridged strategic R&D to manufacturing. Through our unwavering commitment to foster collaboration across the nanoelectronics industry, we help our members and partners address critical industry transitions, drive technical consensus, pull research into the industry mainstream, improve manufacturing productivity, and reduce risk and time to market. Information about SEMATECH can be found at www.sematech.org. Twitter: www.twitter.com/sematech

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Contacts:
Erica McGill
SEMATECH
Marketing Communications
O: 518-649-1041

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